Nvidia

Overview

Participate in ground breaking Processor design and debug in deep submicron technologies and work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.

About Nvidia

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI -- the next era of computing.

Requirements & Eligibility

• BSEE required/MS preferred in Electrical or Electronics Engineering with 8+ years experience
• Good understanding of Design-for-test(DFT) and logic design is required
• Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
• Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it
• Experience in VLSI simulation tools like VCS etc
• Experience with pattern generation using tools such as tessent
• Proficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good

Key Responsibilities

• Participate in ground breaking Processor design and debug in deep submicron technologies
• Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models
• Responsible for generating ATPG patterns for Silicon speed path debug
• RTL and gate level verification for ATPG, non-ATPG patterns
• Correlating diagnosis result to map to real design failures and root cause the same feed learnings to pre-silicon design sign off parameters
• RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon
• Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run
• Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM